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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. june 2009 doc id 15564 rev 1 1/20 20 PM6602 8-row 30-ma led driver with boost regulator, dual dimming mode, smbus interface and dpst for lcd panel backlights features 2 dimming modes: smbus or pwm boost section ? 3.3 v to 28 v input voltage range ? internal power mosfet ? internal +3.3 v ldo for device supply ? up to 36 v output voltage ? constant frequency peak current mode control ? 500 khz to 2 mhz adjustable switching frequency ? pulse-skip power saving mode at light loads ? built-in soft-start feature ? programmable ovp protection ? stable with ceramic output capacitors ? thermal shutdown backlight driver section ? 8 rows with 30 ma maximum current capability (adjustable) ? row disabling option ? 500 ns minimum dimming time (1% minimum dimming duty-cycle at 20 khz) ? 3% current accuracy ? 2% current balance ? led failure (open and short circuit) detection applications backlights of notebook monitors backlights of umpc monitors description the PM6602 consists of a high-efficiency monolithic boost converter and eight controlled current generators (rows), specifically designed to supply led arrays used in the backlights of lcd panels. the device can manage a nominal output voltage of up to 36 v. the generators can be externally programmed to sink up to 30 ma and they can be dimmed in two different modes: via a pwm signal (1% dimming duty-cycle at 20 khz can be managed) or in smbus mode. the device can detect and manage the open and shorted led faults. the device detects the unused rows (connected to sgnd). basic protections (output overvoltage, internal mosfet overcurrent and thermal shutdown) are provided. am0 3 692v1 vfqfpn-24 4x4 table 1. device summary part number package packaging PM6602 vfqfpn-24 4 mm x 4 mm (exposed pad) tu b e PM6602tr tape and reel www.st.com
contents PM6602 2/20 doc id 15564 rev 1 contents 1 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 smbus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PM6602 typical application circuit doc id 15564 rev 1 3/20 1 typical application circuit figure 1. typical application circuit am0 3 69 3 v1 scl jp11 row1 PM6602 comp 1 iset 2 pwmo 3 osc 4 ovp 5 vcc 6 in 7 fault 8 sgnd 9 fb1 10 fb2 11 fb3 12 fb4 13 fb5 14 fb6 15 fb7 16 fb8 17 pgnd 18 lx1 19 pwmi 20 en 21 scl 22 sda 23 dfset 24 thp 25 fb8 rcomp 1k cldo 1u ccomp 20n riset 50k in vcc lx l1 6u8 d1 diode cout1 2u2 cout2 2u2 r1 510k r2 16k fault ovp rf ault 200k ovp d1 led d2 led d3 led d10 led vin jp4 en 1 3 2 vboost en rdf set 50k sgnd fb7_led lx fb6_led sgnd en sgnd fb5_led fb4_led sgnd jp1 pwmo 1 3 2 4 fb3_led sgnd jp3 dfset 1 3 2 4 fb2_led sgnd vboost fb1_led sgnd vcc fb8_led fb7_led fb1_led jp2 osc 1 3 2 fb3 pgnd fb4 cin 4u7 vcc fb6 fb7 pwmi jp18 row8 d2 stps1l40m 1 2 fb5 pwmi jp_in1 2 1 3 fb2 q1 mosfet p fb1 in sgnd fb8_led sda sda jp17 row7 jp0 gnd jp16 row6 sgnd jp15 row5 scl jp14 row4 jp13 row3 rosc 68k jp12 row2 fault
device pinout PM6602 4/20 doc id 15564 rev 1 2 device pinout figure 2. device pinout (top view) table 2. pin description pin # name description 1comp error amplifier output. a simple rc series between this pin and ground is needed to compensate the loop of the boost regulator. 2iset current limit setting for the output generators. the output current of the rows can be programmed by connecting a resistor to sgnd. 3pwmo pwi filter corner frequency selection. leave the pin floating to set 195.6 hz as corner frequency. short directly to gnd to set 12.225 hz. 4osc switching frequency selection. a re sistor to sgnd is used to set the desired switching frequency. 5ovp overvoltage selection. used to set the desired ov threshold by an external resistor divider. 6 vcc +3.3 v ldo output 7 in input voltage. connect to the main supply rail. 8 fault external power mosfet driver output. open drain pin. 9sgnd signal ground. supply return for the analog circuitry and current generators. 10-17 fb1 to fb8 row driver output #1 to row driver out put #8. if a fbx is unused, short the pin to sgnd. 18 pgnd power ground. internal power mosfet ground. 19 lx switching node. drain of the internal power mosfet. 20 pwmi dimming input. used to externally set the brightness by using a pwm signal. 21 en device enable input in pwm dimming mode. unused in smbus mode, to be connected to sgnd. am0 3 694v1 1 3 2 4 6 5 7 9 8 10 12 11 1 8 16 17 15 1 3 14 24 22 2 3 21 19 20 comp i s et pwmo o s c ovp vcc in fault s gnd fb1 fb2 fb 3 df s et s da s cl en pwmi lx pgnd fb 8 fb 7 fb 6 fb 5 fb 4
PM6602 device pinout doc id 15564 rev 1 5/20 22 scl smbus clock 23 sda smbus data 24 dfset dimming frequency selection in smbus mode, using a rusticator to sgnd. directly connect to sgnd to setup the pwm dimming mode table 2. pin description (continued) pin # name description
absolute maximum ratings PM6602 6/20 doc id 15564 rev 1 3 absolute maximum ratings note: solderability specification accord ing to jedec standard #j-std-020d. table 3. absolute maximum ratings (1) 1. stresses beyond those listed under "absolute ma ximum ratings" may cause permanent damage to the device. exposure to absolute maxi mum rated conditions for extended perio ds may affect device reliability. symbol parameter value unit v cc v cc to sgnd -0.3 to 3.6 v pgnd to sgnd -0.3 to 0.3 v in in to pgnd -0.3 to 30 v lx lx to sgnd, lx to pgnd -0.3 to 40 iset, pwmo, ovp, osc, comp, dfset to sgnd -0.3 to v avcc +0.3 en, pwmi to sgnd -0.3 to 6 sda, scl to sgnd -0.3 to 6 fbx to pgnd/sgnd -0.3 to 40 fault to sgnd -0.3 to 30 maximum lx rms current 2.0 a p tot power dissipation t amb = 25 c 2.3 w maximum withstanding voltage range test condition: cdf-aec-q100-002: "human body model" acceptance criteria: "normal performance" tbd (2) 2. esd test to be performed at 2 kv hbm and 200 v mm. kv esd machine model tbd (2) v table 4. thermal data symbol parameter value unit r thja thermal resistance junction to ambient 42 c/w t storage storage temperature range -50 to 150 c t j junction operating temperature range -40 to 125 c t amb operating ambient temper ature range -40 to 85 c
PM6602 absolute maximum ratings doc id 15564 rev 1 7/20 table 5. recommended operating conditions symbol parameter test condition min. typ. max. unit supply section v in input voltage range 3.3 28 v boost section boost supply 3.3 28 v v bst output voltage range 36 f sw adjustable switching frequency osc connected to r fsw 500 2000 khz fbs output maximum current 30 ma pwmi input frequency pwm mode 0.1 30 khz smbus mode 9.5 10 10.5
electrical characteristics PM6602 8/20 doc id 15564 rev 1 4 electrical characteristics table 6. electrical characteristics (v in = 12 v, t amb = t j = 25 c unless otherwise specified) symbol parameter test co ndition min. typ. max. unit supply section i in,q operating quiescent current r iset = 50 k current generators turned off 1ma i in,shdn operating current in shutdown en low and bl_ctl = 0, v in =12v, device off 35 a ldo linear regulator ldo output voltage en high , i ldo =0 ma 3.3 v boost section adjustable switching frequency os c to sgnd with a resistor 500 2000 khz internal power mos r ds(on) 200 m lx leakage current lx = 40 v 5 a peak current limit 2.3 a ov and fault protections v th,ovp hard overvoltage protection reference (ovp) threshold 1.35 v v th,frd floating row detection (ovp) threshold 1.25 v t shdn (1) thermal shutdown turn-off temperature 150 c soft-start and power management en, high level threshold ttl level 2.1 v en, low level threshold ttl level 0.8 pwmi, high level threshold ttl level 2.1 pwmi, low level threshold ttl level 0.8 current generators section fbs current minimum on time riset = 50 k 500 ns t dimmax the time that occurs before the device goes into a new soft-start in case of 0% brightness 30 ms fbs output maximum current 30 ma fbs leakage current 5 a dimming oscillator frequency 100 5000 hz
PM6602 electrical characteristics doc id 15564 rev 1 9/20 smbus interface (smbus follows dell and smbus 2.0 standards) smbus frequency 10 100 khz bus free time 4.7 s start condition hold time from scl 4 start condition setup time from scl 4.7 stop condition setup time from scl 4 sda hold time from scl 300 ns sda setup time from scl 250 scl low period 4.7 s scl high period 4 sda, scl high level threshold ttl level 2.1 v sda, scl low level threshold ttl level 0.8 1. guaranteed by design. table 6. electrical characteristics (v in = 12 v, t amb = t j = 25 c unless otherwise specified) (continued) symbol parameter test co ndition min. typ. max. unit
electrical characteristics PM6602 10/20 doc id 15564 rev 1 4.1 block diagram figure 3. stmafd01 block diagram am0 3 695v1 sgnd + - i to v logic fb1 iset i to v 1.2v current generator 1 int_dim smbus interface & registers thermal shdn control logic & fault management dfset smbus_en digital duty calculation dim generator pwmi sda scl fb2 fb3 fb4 fb5 fb6 fb7 fb8 current gen. 2 v short _th current gen. 3 current gen. 4 current gen. 5 current gen. 6 current gen. 7 current gen. 8 dpst low pass filter pwmo 3.3v ldo vcc uvlo detector in fault in in 50ua boost control logic pgnd lx current sense zcd + - + boost current limit ovp + - gm 0.4v minimum voltage selector comp + - 1.25v slope generator f sw generator osc v fb1 v fb2 v fb3 v fb4 v fb5 v fb6 v fb7 v fb8 ctrl1 ctrl2 ctrl3 ctrl4 ctrl5 ctrl6 ctrl7 ctrl8 ctrl1-8 8 en soft-start control logic
PM6602 smbus interface doc id 15564 rev 1 11/20 5 smbus interface the smbus serial interface is used to turn on the device, monitor faults, set dimming mode and brightness settings and configure the device in general. the address is set to 0x58. no address pin is provided (compliant with dell specifications), nor any rom address configuration. additional configuration bits and registers added for device configuration (other than those specified in the dell specification) include the shorted led threshold (2 bits). the brightness control interface implements the smbus read byte protocol. the brightness control interface implements the smbus write byte protocol. the brightness control interface's smbus component operates correctly when the smbus master clock operates at a frequency of 55 khz. the brightness control interface's smbus component may use clock stretching, but it shall not add more than 10 milliseconds of clock lo w time between any smbus start condition and its corresponding stop. the brightness control interface sends a nak signal (not acknowledge) in response to any smbus operation directed to it that does not use the smbus read byte or write byte protocol. the brightness control interface sends a nak signal in response to any smbus operation directed to it that addresses a register that is not defined in this specification. when the smbus interface is not powered, the smbus interface pins provide a high impedance interface to the bus. read byte as shown in figure 4 , the four-byte-long read byte protocol starts out with the slave address followed by the "command code" which translates to the "register index". then the bus direction turns around with the re-broadcast of the slave address with bit 0 indicating a read ("rd") cycle. the fourth byte contains the data being returned by the backlight controller. that byte value in the data byte should reflect the value of the register being queried at the "command code" index. a dark grey outline is used on cycles during which the backlight controller "owns" or "drives" the data line. all other cycles are driven by the "host". figure 4. read byte protocol note that any other protocol missing the "co mmand code" as implemented in some previous backlight controller devices w ill no longer be supported. am0 3 642v1
smbus interface PM6602 12/20 doc id 15564 rev 1 write byte the write byte protocol is only three bytes long. the first byte starts with the slave address again followed by the "command code" which translates to the "register index" being written. the third byte contains the data byte that must be written into the register selected by the "command code". again note the bus directions as highlighted by the dark grey outline. figure 5. write byte protocol smb clock stretching for special cases where clock stretching must be implemented, the maximum clock stretching allowed is 10 ms cumulative per smb packet (from "start" condition to "stop" condition). smbus register definitions all backlight controller registers are byte-wide and accessible via the read/write_byte protocols. their bit assignments are provided in the following sections with reserved bits containing a default value of "0". brightness control register (0x00) due to the intel ? dpst (display power savings technology) the granularity of the brightness control register is 256 steps. note: brt [7..0] = 256 steps of brightness. specificities of register 0 an smbus write byte cycle to register 0 sets t he brightness level if the backlight controller is in smbus mode. a write byte cycle to register 0 has no effect when the backlight controller is not in smbus mode. an smbus read byte cycle to register 0 returns the current brightness level regardless of the value of pwm_sel. table 7. brightness control register register 0x00 brightness control register brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 bit 7 bit 6 bit 5 bit 3 (r/w) (r/w) (r/w) bit 4 (r/w) (r/w) bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) am0 3 696v1
PM6602 smbus interface doc id 15564 rev 1 13/20 an smbus setting of 0xff for register 0 sets the backlight controller to the maximum brightness output. an smbus setting of 0x00 for register 0 sets the backlight controller to the minimum brightness output. the default value for register 0 is 0xff. device control register (0x01) this register has two bits that control the operating mode of the backlight controller and a single bit that controls the bl on/off state. table 8. register description the pwm_md bit selects the manner in which the pwm input is to be interpreted. when this bit is 0, the pwm input reflects a percen tage change in the current brightness (that is, dpst mode) and should fo llow the following equation. equation 1 where: c bt = current brightness setting from smbus with out influence from the pwm. pwm = percentage of duty cycle the pwm signal starts from 100% when operating in dpst mode. when pwm_md is 1, the pwm input has no effect on the brightness setting unless the backlight controller is in pwm mode. when operating in pwm mode, this bit is a don't care. the pwm_sel bit determines whether the smbus or pwm input should drive the brightness. the relationships between these two control bits can be thought of as specifying an operating mode for the backlight controller. the defined modes are shown in table 10 on page 14 . note: depending on the settings of some bits, other bits have no effect and are "don't care". they are shown with a value of x in ta bl e 1 0 . register 0x00 device control register reserved reserved reserved reserved reserved pwm_md pwm_sel bl_ctl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 (r/w) bit 1 (r/w) bit 0 (r/w) table 9. bit field definitions pwm_md = pwm mode select (1 = absolute brightness, 0 =% change) default = 0 pwm_sel = brightness mux select (1 = pw m pin, 0 = smbus value) default = 0 bl_ctl = bl on/off (1 = on, 0 = off) default = 0 dpst brightness = c bt (pwm)
smbus interface PM6602 14/20 doc id 15564 rev 1 specificities of register 1 all reserved bits return "0" when read. all reserved bits are ignored by the backlight controller when written. all defined control bits return their current, latched value when read. the backlight controller properly handles any smbus write that causes multiple control bits to change value. a value of 1 written to bl_ctl turns on the bl in 10 milliseconds or less after the write cycle completes. the bl is deemed to be on when bit 3 of register 2 is 1. a value of 0 written to bl_ctl immediately turns off the bl. the bl is deemed to be off when bit 3 of register 2 is 0. when an smbus mode is selected, register 0x00 must reflect the last value written to it. however, when any non-smbus mode is selected, register 0x00 must reflect the current brightness value based on the current mode of operation, with the exception of smbus mode with dpst. when smbus mode with dpst is selected, register 0x00 must reflect the last value written from the smbus. when a write to register 1 causes the backlight controller to transition to smbus mode, the brightness of the bl does not change. when a write to register 1 causes the backlight controller to transition to a non-smbus mode, the brightness of the bl changes as appropriate for the new mode. the default value for register 1 is 0x00 fault/status register (0x02) this register has six status bits that allow monitoring the backlight controller's operating state. bit 0 is a logical "or" of all fault codes to simplify error detection. not all of the bits in this register are fault-related - bit 3 is a simp le bl status indicator. all reserved bits must return a "0" when read and ignore the bit value when written. all bits in this register are read- only. table 10. backlight controller modes selected by device control register bits 1 & 2 pwm_md pwm_sel mode x 1 pwm mode 1 0 smbus mode 0 0 smbus mode with dpst table 11. register description register 0x02 fault/status register reserved reserved 2_ch_sd 1_ch_sd bl_stat ov_curr thrm_shdn fault bit 7 (r) bit 6 (r) bit 5 (r) bit 4 (r) b it 3 (r) bit 2 (r) bit 1 (r) bit 0 (r)
PM6602 smbus interface doc id 15564 rev 1 15/20 specificities of register 2 all reserved bits return "0" when read. a write byte cycle to register 2 has no effect. this register is read-only. a read byte cycle to register 2 always indicates the current bl on/off status in bl_stat (1 if the bl is on, 0 if the bl is off). a read byte cycle to register 2 always returns fault as the logical or of thrm_shdn and ov_curr and 1_ch_sd and 2_ch_sd only (bits 1, 2, 4 and 5). the thrm_shdn bit is optional. if not implemented it always returns 0 when read. if implemented, the value of thrm_shdn is 1 when the backlight controller shuts down due to a thermal event. in all othe r cases the value of thrm_shdn is 0. the value of ov_curr is 1 when the backlight controller shuts down due to an input over- current event. in all other cases, the value of ov_curr is 0. a fault does not occur or is not reported when the bl is commanded on and immediately off by the system. the value of bl_stat is 1 whenever the bl is on. the value of bl_stat is 0 whenever the bl is off. the default value for register 2 is 0x00. when fault is set to 1, it is cleared when the bl_ctl bit of the device control register is toggled. at that time, if the fault condition is still present or reoccurs, fault is again set to 1. the device does not indicate a fault if the voltage vbl+ is removed, regardless of whether or not the bl was on at the time of the power loss. in the event that the controller shuts down due to an over-current fault or other fault condition, the controller cannot re-sta rt until a power cycle of vbl+ occurs. table 12. bit field definitions bit num. description value bit 5 2_ch_sd the number of faulted strings is reported in bits 5 and 4. (00 = no faults, 01 = one string fault, 11 = two or more string faults) bit 4 1_ch_sd bit 3 bl_stat bl status (1 = bl on, 0 = bl off) bit 2 ov_curr input over-current (1 = ov er-current condition, 0 = current ok) bit 1 thrm_shdn thermal shutdown (1 = thermal fault, 0 = thermal ok) bit 0 fault fault occurred (logic "or" of all of the fault conditions)
smbus interface PM6602 16/20 doc id 15564 rev 1 identification register (0x03) the id register contains two bit fields to denote the manufactur er and the silicon revision of the controller ic. specificities of register 3 a write byte cycle to register 3 has no effect. this register is read-only. the value of mfg is 5 for the st device. configuration register (0x04) the id register contains two bit fields to set the shorted led voltage threshold. three different values are available. note: vth0, vth1 = shorted le d threshold selection bits. table 13. register description register 0x03 id register led panel mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 bit 7=1 bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) table 14. bit field definitions mfg [3..0] manufacturer id=5+st (a ccording to dell specifications) rev [2..0] silicon rev (revs 0-7 allowed for silicon spins) table 15. register description register 0x03 id register reserved reserved reserved reserved reserved reserved vth1 vth0 bit 7=1 bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r/w) bit 0 (r/w) table 16. backlight controller modes vth1 vth0 mode 0 0 default value v fbx,fault =8 v 10v fbx,fault =2 v 01v fbx,fault =3.3 v 1 1 no protection
PM6602 package mechanical data doc id 15564 rev 1 17/20 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 17. vfqfpn-24 mechanical data dim. min typ max a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d 3.85 4.00 4.15 d2 2.5 2.6 2.7 e 3.85 4.00 4.15 e2 2.5 2.6 2.7 e0.50 l 0.30 0.40 0.50 ddd 0.08
package mechanical data PM6602 18/20 doc id 15564 rev 1 figure 6. vfqfpn-24 mechanical data
PM6602 revision history doc id 15564 rev 1 19/20 7 revision history table 18. document revision history date revision changes 03-june-2009 1 initial release.
PM6602 20/20 doc id 15564 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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